74F374 datasheet(6/12 Pages) PHILIPS

6 / 12 page

Philips Semiconductors

Product specification

74F373/74F374

Latch/flip-flop

December 5, 1994

DC ELECTRICAL CHARACTERISTICS

(Over recommended operating free-air temperature range unless otherwise noted.)

SYMBOL

PARAMETER

TEST

LIMITS

UNIT

SYMBOL

PARAMETER

CONDITIONS1

MIN

TYP2

MAX

UNIT

High level output voltage

VCC = MIN, VIL = MAX,

±10%VCC

2.4

VOH

High-level output voltage

VIH = MIN, IOH = MAX

±5%VCC

2.7

3.4

Low level output voltage

VCC = MIN, VIL = MAX,

±10%VCC

0.35

0.50

VOL

Low-level output voltage

VIH = MIN, IOL = MAX

±5%VCC

0.35

0.50

VIK

Input clamp voltage

VCC = MIN, II = IIK

-0.73

-1.2

Input current at maximum input voltage

VCC = MAX, VI = 7.0V

100

µA

IIH

High-level input current

VCC = MAX, VI = 2.7V

µA

IIL

Low-level input current

VCC = MAX, VI = 0.5V

-0.6

IOZH

Off-state output current, high-level voltage applied

VCC = MAX, VO = 2.7V

µA

IOZL

Off-state output current, low-level voltage applied

VCC = MAX, VO = 0.5V

-50

µA

IOS

Short-circuit output current3

VCC = MAX

-60

-150

ICC

Supply current (total)

74F373

VCC = MAX

ICC

Supply current (total)

74F374

VCC = MAX

NOTES:

1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.

2. All typical values are at VCC = 5V, Tamb = 25°C.

3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting

of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any

sequence of parameter tests, IOS tests should be performed last.

AC ELECTRICAL CHARACTERISTICS

LIMITS

Tamb = +25°C

Tamb = 0°C to +70°C

SYMBOL

PARAMETER

TEST

VCC = +5.0V

VCC = +5.0V ± 10%

UNIT

CONDITION

CL = 50pF, RL = 500Ω

MIN

TYP

MAX

MIN

MAX

tPLH

tPHL

Propagation delay

Dn to Qn

Waveform 3

3.0

2.0

5.3

3.7

7.0

5.0

3.0

2.0

8.0

6.0

tPLH

tPHL

Propagation delay

E to Qn

74F373

Waveform 2

5.0

3.0

9.0

4.0

11.5

7.0

5.0

3.0

12.0

8.0

tPZH

tPZL

Output enable time

to high or low level

Waveform 6

Waveform 7

2.0

5.0

5.6

11.0

7.5

2.0

11.5

8.5

tPHZ

tPLZ

Output disable time

from high or low level

Waveform 6

Waveform 7

2.0

4.5

3.8

6.5

5.0

2.0

7.0

6.0

fmax

Maximum clock frequency

Waveform 1

150

165

140

tPLH

tPHL

Propagation delay

CP to Qn

74F374

Waveform 1

3.5

5.0

7.5

3.0

8.5

tPZH

tPZL

Output enable time

to high or low level

Waveform 6

Waveform 7

2.0

9.0

5.3

11.0

7.5

2.0

12.0

8.5

tPHZ

tPLZ

Output disable time

from high or low level

Waveform 6

Waveform 7

2.0

5.3

4.3

6.0

5.5

2.0

7.0

6.5

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