74F3893 datasheet(2/10 Pages) PHILIPS

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Philips Semiconductors

Product specification

74F3893

Quad Futurebus backplane transceiver

January 18, 1991

853-1397 01496

FEATURES

• Quad backplane transceiver

• Drives heavily loaded backplanes with equivalent load

impedances down to 10 ohms

• Futurebus drivers sink 100mA

• Reduced voltage swing (1 volt) produces less noise and

reduces power consumption

• High speed operation enhances performance of backplane

buses and facilitates incident wave switching

• Compatible with IEEE 896 and IEEE 1194.1 Futurebus

Standards

• Built–in precision band–gap (BG) reference provides

accurate receiver thresholds and improved noise immunity

• Glitch–free power up/power down operation on all outputs

• Pin and function compatible with NSC DS3893

DESCRIPTION

The 74F3893 is a quad backplane transceivers and is

intended to be used in very high speed bus systems.

The 74F3893 interfaces to ‘Backplane Transceiver Logic’

(BTL). BTL features a reduced (1V to 2V) voltage swing for

lower power consumption and a series diode on the drivers

to reduce capacitive loading (< 5pF).

Incident wave switching is employed, therefore BTL

propagation delays are short. Although the voltage swing is

much less for BTL, so is its receiver threshold region,

therefore noise margins are excellent.

BTL offers low power consumption, low ground bounce, EMI

and crosstalk, low capacitive loading, superior noise margin

and low propagation delays. This results in a high

bandwidth, reliable backplane.

The 74F3893 has four TTL outputs (Rn) on the receiver

side with a common receiver enable input (RE). It has four

data inputs (Dn) which are also TTL. These data inputs are

NANDed with the data enable input (DE). The four I/O pins

(bus side) are futurebus compatible, sink a minimum of

100mA, and are designed to drive heavily loaded

backplanes with load impedances as low as 10 ohms. All

outputs are designed to be glitch–free during power up and

down.

TYPE

TYPICAL

PROPAGATION DELAY

TYPICAL SUPPLY

CURRENT( TOTAL)

74F3893

3.0ns

55mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

VCC = 5V ±10%,

Tamb = 0°C to +70°C

PKG DWG #

20-pin PLCC

N74F3893A

SOT380-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 – D3

Data inputs

1.0/0.067

µA/40µA

Data enable input

1.0/0.33

µA/200µA

Receiver enable input

1.0/0.067

µA/40µA

I/O0 – I/O3

Bus inputs

5.0/0.033

100

µA/20µA

I/O0 – I/O3

Bus outputs

OC/166.7

OC/100mA

R0 – R7

Receiver outputs

150/40

3mA/24mA

Notes to input and output loading and fan out table

One (1.0) FAST unit load is defined as: 20

µA in the high state and 0.6mA in the low state.

OC= Open collector.

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