Philips Semiconductors

Product specification

74F647/74F649

Octal transceivers/registers (open-collector)

1992 Feb 28

4

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

A0 - A7

A inputs

1.0/0.033

20

µA/20µA

B0 - B7

B inputs

1.0/0.033

20

µA/20µA

CPAB

A-to-B clock input

1.0/0.033

20

µA/20µA

CPBA

B-to-A clock input

1.0/0.033

20

µA/20µA

SAB

A-to-B select input

1.0/0.033

20

µA/20µA

SBA

B-to-A select input

1.0/0.033

20

µA/20µA

DIR

Data flow Directional control enable input

1.0/0.066

20

µA/20µA

OE

Output Enable input

1.0/0.066

20

µA/20µA

A0 - A7

A outputs

OC/106.7

OC/64mA

B0 - B7

B outputs

OC/106.7

OC/64mA

NOTE:

One (1.0) FAST Unit Load is defined as: 20

µA in the High state and 0.6mA in the Low state. OC = Open Collector

FUNCTION TABLE

INPUTS

DATA I/O

OPERATING MODE

OE

DIR

CPAB

CPBA

SAB

SBA

A0-A7

B0-B7

X

X

↑

X

X

X

Input

Unspecified*

Store A, B unspecified*

Store A, B unspecified*

X

X

X

↑

X

X

Unspecified*

Input

Store B, A unspecified*

Store B, A unspecified*

H

H

X

X

↑

H or L

↑

H or L

X

X

X

X

Input

Input

Store A and B data

Isolation, hold storage

Store A and B data

Isolation, hold storage

L

L

L

L

X

X

X

H or L

X

X

L

H

Output

Input

Real time B data to A bus

Stored B data to A bus

Real time B data to A bus

Stored B data to A bus

L

L

H

H

H or L

X

X

X

L

H

X

X

Input

Output

Real time A data to B bus

Stored A data to B bus

Real time A data to B bus

Stored A data to B bus

H = High voltage level

L

= Low voltage level

X = Don’t care

↑ = Low-to-High clock transition

*

= The data output function may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always

enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.

LOGIC DIAGRAM – 74F647

C1

1 of 8 Channels

1D

C1

1D

21

3

23

22

1

2

OE

DIR

CPBA

SBA

CPAB

SAB

To 7 other channels

A0

B0

4

20

SF01202

LOGIC DIAGRAM – 74F649

C1

1 of 8 Channels

1D

C1

1D

21

3

23

22

1

2

OE

DIR

CPBA

SBA

CPAB

SAB

To 7 other channels

A0

B0

4

20

SF01203