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74F777 Datasheet(PDF) 2 Page - NXP Semiconductors

Part # 74F777
Description  Triple bidirectional latched bus transceiver 3-State open collector
PDF  12 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74F777 Datasheet(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74F777
Triple bidirectional latched bus transceiver (3–State +
Open Collector)
2
May 19, 1992
853–1645 06772
FEATURES
• Latching transceiver
• High drive Open Collector output current with minimum output
swing
• Compatible with Test Mode (TM) bus specification
• Controlled output ramp
• Multiple package options
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F777 is a triple bidirectional latched bus transceiver and is
intended to provide the electrical interface to a high performance
wired–OR bus. This bus has a loaded characteristics impedance
range of 20 to 50 ohms and is terminated on each end with a 30 to
40 ohm resistor.
The 74F777 is a triple bidirectional transceiver with Open Collector
B and 3–State A port output drivers. A latch function is provided for
the A port signals. The B port output driver is designed to sink
100mA from 2 volts to minimize crosstalk and ringing on the bus.
A separate output threshold clamp voltage (VX) is provided to
prevent the A port output High level from exceeding future high
density processor supply voltage levels. For 5 volt systems, VX is
simply tied to VCC.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY CUR-
RENT( TOTAL)
74F777
7.0ns
45mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
INDUSTRIAL RANGE
PKG DWG #
VCC = 5V ±10%, Tamb = 0°C to +70°C
VCC = 5V ±10%,
Tamb = –40°C to +85°C
20–pin plastic DIP (300 mil)
N74F777N
I74F777N
SOT146-1
20–pin PLCC
N74F777A
I74F777A
SOT380-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A2
PNP latched inputs
3.5/0.117
70
µA/70µA
B0 – B2
Data inputs with threshold circuitry
5.0/0.167
100
µA/100µA
OEA0 – OEA2
A output enable inputs (active–High)
1.0/0.033
20
µA/20µA
OEB0 – OEB2
B output enable inputs (active–Low)
1.0/0.033
20
µA/20µA
LE0 – LE2
Latch enable inputs (active–Low)
1.0/0.033
20
µA/20µA
A0 – A2
3–State outputs
150/40
3mA/24mA
B0 – B2
Open Collector outputs
OC/166.7
OC/100mA
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20
µA in the High state and 0.6mA in the Low state.
OC = Open Collector.



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