STRT71XF datasheet(13/74 Pages) STMICROELECTRONICS

13 / 74 page

STR71xF

Introduction

13/74

P2.4/A.20

I/O

8mA

Port 2.4

External Memory Interface: address

bus

P2.5/A.21

I/O

8mA

Port 2.5

P2.6/A.22

I/O

8mA

Port 2.6

BOOTEN

Boot control input. Enables sampling of

BOOT[1:0] pins

P2.7/A.23

I/O

8mA

Port 2.7

External Memory Interface: address

bus

P2.8

I/O pu

CT X 4mA X

Port 2.8

External interrupt INT2

N.C.

Not connected (not bonded)

N.C.

Not connected (not bonded)

VSS

Ground voltage for digital I/Os4)

V33

Supply voltage for digital I/Os4)

P2.9

I/O pu

CT X 4mA X

Port 2.9

External interrupt INT3

P2.10

I/O pu

CT X 4mA X

Port 2.10

External interrupt INT4

P2.11

I/O pu

CT X 4mA X

Port 2.11

External interrupt INT5

P2.12

I/O pu

4mA

Port 2.12

P2.13

I/O pu

4mA

Port 2.13

P2.14

I/O pu

4mA

Port 2.14

P2.15

I/O pu

4mA

Port 2.15

JTDI

JTAG Data input. External pull-up required.

JTMS

JTAG Mode Selection Input. External pull-up

required.

JTCK

JTAG Clock Input. External pull-up or pull-down

required.

JTDO

8mA

JTAG Data output. Note: Reset state = HiZ.

JTRST

JTAG Reset Input. External pull-up required.

Reserved, must be forced to ground.

TEST

Reserved, must be forced to ground.

N.C.

Not connected (not bonded)

TEST

Reserved, must be forced to ground.

N.C.

Not connected (not bonded)

Table 3.

STR710 Pin Description

Pin n°

Pin Name

Input

Output

Main

function

(after

reset)

Alternate function

STRT71XF Datasheet(PDF) 13 Page - STMicroelectronics

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