Philips Semiconductors

Product specification

74F835

8-bit shift register with 2:1 mux-in,

latched “B” inputs, and serial out

1990 Jan 08

3

LOGIC DIAGRAM

GND = PIN 12

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

D

Q

CP

11

Q7

D

E

Q

D

E

Q

D

E

Q

D

E

Q

D

E

Q

D

E

Q

D

E

Q

D

E

Q

16

17

18

19

20

21

22

23

3

4

5

6

7

8

9

10

D0A

D0B

D1A

D1B

D2A

D2B

D3A

D3B

D4A

D4B

D5A

D5B

D6A

D6B

D7A

D7B

LE

13

14

1

15

2

SA/B

PE

DS

CP

SF01358

FUNCTION TABLE

OPERATING

MODE

INPUTS

INTERNAL

OUTPUT

OPERATING

MODE

INPUTS

B

LATCH

SERIAL REGISTER

OUTPUT

MODE

PE

CP

LE

SA/B

DnA

DnB

DS

B

LATCH

Q0

Q1–6

Q7

Parallel load

A data

L

↑

X

L

h

X

X

X

H

H

H

Parallel load

A data

L

↑

X

L

l

X

X

X

L

L

L

Latch B data

X

X

L

X

X

h

X

H

X

X

X

Latch B data

X

X

L

X

X

l

X

L

X

X

X

Parallel load B data

(from Latch)

L

↑

L

H

X

X

X

h

H

H

H

Parallel load B data

(from Latch)

L

↑

L

H

X

X

X

l

L

L

L

Parallel load B data

(Transparent Mode)

L

↑

H

H

X

h

X

h

H

H

H

Parallel load B data

(Transparent Mode)

L

↑

H

H

X

l

X

l

L

L

L

Serial Shift

H

↑

X

X

X

X

h

X

H

qn–1

q6

Serial Shift

H

↑

X

X

X

X

l

X

L

qn–1

q6

H = High voltage level

L

= Low voltage level

h

= High voltage level one setup time prior to the Low-to-High clock transition

l

= Low voltage level one setup time prior to the Low-to-High clock transition

X = Don’t care

qn = Lower case letters indicate the state of the referenced flop cell one cycle prior to the Low-to-High clock transition

↑ = Low-to-High clock transition