74HC4050 datasheet(2/7 Pages) PHILIPS

2 / 7 page

December 1990

Philips Semiconductors

Product speciﬁcation

Hex high-to-low level shifter

74HC4050

FEATURES

• Output capability: standard

• ICC category: SSI

GENERAL DESCRIPTION

The 74HC4050 is a high-speed Si-gate CMOS device and

is pin compatible with the “4050” of the “4000B” series. It

is specified in compliance with JEDEC standard no. 7A.

The 74HC4050 provides six non-inverting buffers with a

modified input protection structure, which has no diode

connected to VCC. Input voltages of up to 15 V may

therefore be used. This feature enables the non-inverting

buffers to be used as logic level translators, which will

convert high level logic to low level logic, while operating

from a low voltage power supply. For example 15 V logic

(“4000B series”) can be converted down to 2 V logic.

The actual input switch level remains related to the VCC

and is the same as mentioned in the family characteristics.

APPLICATIONS

• Converting 15 V logic (“4000B” series) down to 2 V logic.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in V

∑ (CL × VCC2 × fo) = sum of outputs

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL / tPLH

propagation delay nA to nY

CL = 15 pF; VCC = 5 V

input capacitance

3.5

CPD

power dissipation capacitance per buffer

note 1

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