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CMOS High Voltage Logic - MM74C906M

Rev 1.0

16/07/2021

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

CMOS TO CMOS

VCC = 5V

3.5

-

-

V

Logical “1” Input Voltage

VIN(1)

VCC = 10V

8.0

-

-

V

VCC = 5V

-

-

1.5

V

Logical “0” Input Voltage

VIN(0)

VCC = 10V

-

-

2.0

V

Logical “1” Input Current

IIN(1)

VCC = 15V, VIN = 15V

-

0.005

1

µA

Logical “0” Input Current

IIN(0)

VCC = 15V, VIN = 0V

-1.0

-0.005

-

µA

Supply Current

ICC

VCC = 15V,Output Open

-

0.05

15

µA

Output Leakage Current

VCC = 4.75V,

VIN = VCC – 1.5V,

VCC=4.75V,VOUT =18V

-

0.005

5

µA

CMOS/LPTTL INTERFACE

Logical “1” Input Voltage

VIN(1)

VCC = 4.75V

VCC

-1.5V

-

-

V

Logical “0” Input Voltage

VIN(0)

VCC = 4.75V

-

-

0.8

V

OUTPUT DRIVE CURRENT

VCC = 4.75V,

VIN = 1V + 0.1 VCC,

2.1

VCC=4.75V,VOUT =0.5V

8.0

-

mA

VCC = 4.75V,

VIN = 1V + 0.1 VCC,

VCC=4.75V,VOUT =1.0V

4.2

12.0

-

mA

VCC = 10V, VIN = 2V,

VCC= 10V,VOUT =0.5V

4.2

20

-

mA

VCC = 10V, VIN = 2V,

VCC= 10V,VOUT =1V

8.4

30

-

mA

DC Electrical Characteristics T

A = -40 to +85°C unless otherwise stated

Dynamic Electrical Characteristics2 T

A = 25°C unless otherwise stated

PARAMETER

SYMBOL

TEST

CONDITIONS

MIN

TYP

MAX

UNITS

Propagation Delay Time

to Logical “0”

tpd

VCC = 5.0V,

R = 10kΩ, CL = 50pF

-

-

150

ns

Propagation Delay Time

to Logical “1”

tpd

VCC = 10V,

R = 10kΩ, CL = 50pF

-

-

75

ns

Input Capacitance

CIN

-

-

5.0

-

pF

Output Capacitance

COUT

-

-

20

-

pF

Power Dissipation Capacitance

2

CPD

-

-

30

-

pF

2. Per Buffer, used to determine the no-load dynamic power consumption: PD = CPD VCC

2f + ICC VCC.

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