September 1993

2

Philips Semiconductors

Product specification

3-to-8 line decoder/demultiplexer; inverting

74HC/HCT138

FEATURES

• Demultiplexing capability

• Multiple input enable for easy expansion

• Ideal for memory chip select decoding

• Active LOW mutually exclusive outputs

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT138 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT138 decoders accept three binary

The “138” features three enable inputs: two active LOW

This multiple enable function allows easy parallel

expansion of the “138” to a 1-of-32 (5 lines to 32 lines)

decoder with just four “138” ICs and one inverter.

The ”138” can be used as an eight output demultiplexer by

using one of the active LOW enable inputs as the data

input and the remaining enable inputs as strobes. Unused

enable inputs must be permanently tied to their

appropriate active HIGH or LOW state.

The ”138” is identical to the “238” but has inverting outputs.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

12

17

ns

14

19

ns

input capacitance

3.5

3.5

pF

power dissipation capacitance per package

notes 1 and 2

67

67

pF