74HC139D datasheet(2/7 Pages) PHILIPS

2 / 7 page

September 1993

Philips Semiconductors

Product speciﬁcation

Dual 2-to-4 line decoder/demultiplexer

74HC/HCT139

FEATURES

• Demultiplexing capability

• Two independent 2-to-4 decoders

• Multifunction capability

• Active LOW mutually exclusive outputs

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT139 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). It is specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT139 are high-speed, dual 2-to-4 line

decoder/multiplexers. This device has two independent

decoders, each accepting two binary weighted inputs

(nA0 and nA1) and providing four mutually exclusive active

LOW outputs (nY0 to nY3). Each decoder has an active

LOW enable input (nE).

When nE is HIGH, every output is forced HIGH. The

enable can be used as the data input for a 1-to-4

demultiplexer application.

The “139” is identical to the HEF4556 of the HE4000B

family.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

APPLICATIONS

• Memory decoding or data-routing

• Code conversion

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC = 5 V

nAn to nYn

nE3 to nYn

input capacitance

3.5

CPD

power dissipation capacitance per multiplexer

notes 1 and 2

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