74HC154 datasheet(2/7 Pages) PHILIPS

2 / 7 page

September 1993

Philips Semiconductors

Product speciﬁcation

4-to-16 line decoder/demultiplexer

74HC/HCT154

FEATURES

• 16-line demultiplexing capability

• Decodes 4 binary-coded inputs into one of 16 mutually

exclusive outputs

• 2-input enable gate for strobing or expansion

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT154 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT154 decoders accept four active HIGH

binary address inputs and provide 16 mutually exclusive

active LOW outputs.

The 2-input enable gate can be used to strobe the decoder

to eliminate the normal decoding “glitches” on the outputs,

or it can be used for the expansion of the decoder.

The enable gate has two AND’ed inputs which must be

LOW to enable the outputs.

The “154” can be used as a 1-to-16 demultiplexer by using

one of the enable inputs as the multiplexed data input.

When the other enable is LOW, the addressed output will

follow the state of the applied data.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay An, En to Yn

CL = 15 pF; VCC =5 V

input capacitance

3.5

CPD

power dissipation capacitance per package

notes 1 and 2

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