PIC16F15213 datasheet(108/439 Pages) MICROCHIP

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15.1

Program Flash Memory (PFM)

The Program Flash Memory (PFM) is readable, writable and erasable over the entire VDD range.

PFM consists of the following regions:

• User program memory (read/write)

• Configuration Words (read/write)

• Device ID (read-only)

• Revision ID (read-only)

• User ID (read-write)

• Device Information Area (read-only)

• Device Configuration Information (read-only)

PFM can be read and/or written to through:

• CPU instruction fetch (read-only)

• FSR/INDF indirect access (read-only)

• NVMREG access (read-write)

• In-Circuit Serial Programming

™ (ICSP™) (external read-write)

It is important to understand the program memory structure for erase and programming operations. Program memory

is arranged in rows. A row consists of 32 14-bit program memory words. A row is the minimum size that can be

erased by user software. A Bulk Erase command cannot be issued from user code.

Read operations return a single word of memory. Write and erase operations are done on a row basis. Program

memory will erase to a logic ‘1’ and program to a logic ‘0’.

All or a portion of a row can be programmed. Data to be written into the program memory row is written to 14-bit

wide data write latches. These latches are not directly accessible, but may be loaded via sequential writes to the

NVMDATH:NVMDATL register pair.

Important: To modify only a portion of a previously programmed row, the contents of the entire row must

be read. Then, the new data and retained data can be written into the write latches to reprogram the row

of program memory. However, any unprogrammed locations can be written without first erasing the row. In

this case, it is not necessary to save and rewrite the other previously programmed locations.

Writing or erasing program memory will cease instruction fetches until the operation is complete. The program

memory cannot be accessed during the write or erase, so code cannot execute. An internal programming timer

controls the write time of program memory writes and erases.

A value written to program memory does not need to be a valid instruction. Executing a program memory location

that forms an invalid instruction results in a NOP.

15.1.1

FSR and INDF Access

The File Select (FSR) and INDF registers allow indirect access to the Program Flash Memory. Indirect addressing

is a mode in which the memory address in the instruction is determined by another register. The value of the FSR

registers is used to determine the memory address location to be accessed.

15.1.1.1 FSR Read

The FSRs are used to provide read access to program memory.

Program memory is accessed by loading the FSRxH:FSRxL register pair with the address to be read, and setting

bit 7 of the FSRxH register to ‘1’. When a MOVIW instruction, or any instruction that accesses INDFx, is executed,

the value loaded into the FSRx register pair points to the location in program memory to be accessed. If the FSRx

Reading from NVM requires one instruction cycle. The CPU operation is suspended during the read and resumes

immediately after. Read operations return a single byte of memory.

PIC16F15213/14/23/24/43/44

NVM - Nonvolatile Memory Control

and its subsidiaries

Data Sheet

DS40002195E-page 108

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