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PIC16F15213 Datasheet(PDF) 110 Page - Microchip Technology |
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PIC16F15213 Datasheet(HTML) 110 Page - Microchip Technology |
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110 / 439 page ![]() 15.1.2.2 NVM Unlock Sequence The unlock sequence is a mechanism that protects the NVM from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: • PFM Row Erase • Write of PFM write latches to PFM memory • Write of PFM write latches to User IDs • Write to Configuration Words The unlock sequence consists of the following steps and must be completed in order: • Write 55h to NVMCON2 • Write AAh to NMVCON2 • Set the WR bit Once the WR bit is set, the processor will stall internal operations until the operation is complete and then resume with the next instruction. Since the unlock sequence must not be interrupted, global interrupts must be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. Figure 15-2. NVM Unlock Sequence Filename: 10-000047B.vsd Title: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Last Edit: 8/24/2015 First Used: PIC15F1508/9 Note: Start Unlock Sequence End Unlock Sequence Write 0x55 to NVMCON2 Write 0xAA to NVMCON2 Initiate Write or Erase operation (WR = 1) Rev. 10-000047B 8/24/2015 Example 15-2. NVM Unlock Sequence NVMCON1bits.WREN = 1; // Enable write/erase INTCONbits.GIE = 0; // Disable global interrupts // The next three steps are the required unlock sequence NVMCON2 = 0x55; // First unlock code NVMCON2 = 0xAA; // Second unlock code NVMCON1bits.WR = 1; // Initiate write/erase cycle INTCONbits.GIE = 1; // Enable global interrupts NVMCON1bits.WREN = 0; // Disable further write/erase cycles PIC16F15213/14/23/24/43/44 NVM - Nonvolatile Memory Control © 2020-2022 Microchip Technology Inc. and its subsidiaries Data Sheet DS40002195E-page 110 |
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