74HC173N datasheet(2/10 Pages) PHILIPS

2 / 10 page

December 1990

Philips Semiconductors

Product speciﬁcation

Quad D-type ﬂip-ﬂop; positive-edge trigger; 3-state

74HC/HCT173

FEATURES

• Gated input enable for hold (do nothing) mode

• Gated output enable control

• Edge-triggered D-type register

• Asynchronous master reset

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT173 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT173 are 4-bit parallel load registers with

clock enable control, 3-state buffered outputs (Q0 to Q3)

and master reset (MR).

When the two data enable inputs (E1 and E2) are LOW, the

data on the Dn inputs is loaded into the register

synchronously with the LOW-to-HIGH clock (CP)

transition. When one or both En inputs are HIGH one

set-up time prior to the LOW-to-HIGH clock transition, the

enable inputs are fully edge-triggered and must be stable

only one set-up time prior to the LOW-to-HIGH clock

transition.

The master reset input (MR) is an active HIGH

asynchronous input. When MR is HIGH, all four flip-flops

are reset (cleared) independently of any other input

condition.

The 3-state output buffers are controlled by a 2-input NOR

gate. When both output enable inputs (OE1 and OE2) are

LOW, the data in the register is presented to the Qn

outputs. When one or both OEn inputs are HIGH, the

outputs are forced to a high impedance OFF-state. The

3-state output buffers are completely independent of the

clock and reset operations.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf =6ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC −1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay

CP to Qn

MR to Qn

CL = 15 pF; VCC =5V

fmax

maximum clock frequency

MHz

input capacitance

3.5

CPD

power dissipation

capacitance per ﬂip-ﬂop

notes 1 and 2

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