M5M29KB/T331AVP

Renesas LSIs

Rev.1.0_48a_bezz

18

33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

Flash VCC Power up / down Timing

AC Waveforms for Read Operation and Test Conditions

t

PS

3.3V

GND

V

CC

V

IH

RP#

Read /Write Inhibit

t

VCS

CE#

WE#

Read /Write Inhibit

V

IL

V

IH

V

IL

V

IH

V

IL

t

PS

Read /Write Inhibit

TEST CONDITIONS

FOR AC CHARACTERISTICS

Input Voltage : V

Input Rise and Fall Times : <5ns

Reference Voltage

at timing measurement : (Vcc)/2

Output Load : 1 TTL gate +

CL(30pF)

or

Output Valid

CE#

OE#

WE#

DATA

Address Valid

High-Z

DUT

3.3kohm

1N914

1.3V

CL=30pF

RP#

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

High-Z

V

OH

V

O

V

IH

V

IL

FFH

CL=30pF

- After inputting Read Array Command FFH, it is necessary to make CE# “H” pulse more than 30ns (tCEPH).

And after inputting Read Array Command FFH, it is also necessary to keep 30ns to recover before starting read

after WE# rises “H” in case of changing address(es) and CE#=“L”.