LIS2DUX12 datasheet(9/102 Pages) STMICROELECTRONICS

9 / 102 page

2.4.2

I²C - inter-IC control interface

Subject to general operating conditions for Vdd and Top.

Table 6. I²C slave timing values

Symbol

Parameter

I²C fast mode(1)(2)

I²C fast mode plus(1)(2)

Unit

Min

Max

Min

Max

f(SCL)

SCL clock frequency

400

1000

kHz

tw(SCLL) SCL clock low time

1.3

0.5

µs

tw(SCLH) SCL clock high time

0.6

0.26

tsu(SDA)

SDA setup time

100

th(SDA)

SDA data hold time

0.9

µs

th(ST)

START/REPEATED START condition hold time

0.6

0.26

tsu(SR)

REPEATED START condition setup time

0.6

0.26

tsu(SP)

STOP condition setup time

0.6

0.26

tw(SP:SR) Bus free time between STOP and START condition

1.3

0.5

Data valid time

0.9

0.45

Data valid acknowledge time

0.9

0.45

Capacitive load for each bus line

400

550

1. Data based on standard I²C protocol requirement, not tested in production.

2. Data for I²C fast mode and I²C fast mode plus have been validated by characterization, not tested in production.

Figure 5. I²C slave timing diagram

tsu(SP)

tw(SCLL)

tsu(SDA)

tsu(SR)

th(ST)

tw(SCLH)

th(SDA)

tw(SP:SR)

START

REPEATED

START

STOP

SDA

SCL

Note:

Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports.

LIS2DUX12

Communication interface characteristics

DS14071 - Rev 2

page 9/102

LIS2DUX12 Datasheet(PDF) 9 Page - STMicroelectronics

LIS2DUX12 Datasheet(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL