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TLK2201BRCP Datasheet(PDF) 12 Page - Texas Instruments |
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TLK2201BRCP Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 21 page ![]() TLK2201B, TLK2201BI ETHERNET TRANSCEIVERS SLLS585 − NOVEMBER 2003 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 transmitter/receiver characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vod = |TxD−TxN| Rt = 50 Ω 600 850 1100 mV Vod = |TxD−TxN| Rt = 75 Ω 800 1050 1200 mV V(cm) Transmit common mode voltage range Rt = 50 Ω 1000 1250 1400 mV V(cm) Transmit common mode voltage range Rt = 75 Ω 1000 1250 1400 mV Receiver Input voltage requirement, Vid = |RxP − RxN| 200 1600 mV Receiver common mode voltage range, (RxP + RxN)/2 1000 1250 2250 mV Ilkg(R) Receiver input leakage current −350 350 µA CI Receiver input capacitance 2 pF t(TJ) Serial data total jitter (peak-to-peak) Differential output jitter, Random + deterministic, PRBS pattern, Rω = 125 MHz 0.24 UI t(DJ) Serial data deterministic jitter (peak-to-peak) Differential output jitter, PRBS pattern, Rω = 125 MHz 0.12 UI tr, tf Differential signal rise, fall time (20% to 80%) RL = 50 Ω, CL = 5 pF, See Figures 7 and 8 100 250 ps Serial data jitter tolerance minimum required eye opening, (per IEEE-802.3 specification) Differential input jitter, Random + deterministic, Rω = 125 MHz 0.25 UI Receiver data acquisition lock time from powerup 500 µs Data relock time from loss of synchronization 1024 Bit times td(Tx latency) Tx latency TBI modes See Figure 1 19 20 UI td(Tx latency) Tx latency DDR mode 29 30 UI td(Rx latency) Rx latency TBI modes See Figure 6 21 31 UI td(Rx latency) Rx latency DDR mode 27 34 UI 80% 50% 20% tr tr tf tf 80% 50% 20% ∼ V ∼ V ∼ V ∼ V 80% 20% 0 V ∼ 1V ∼ −1V TX+ TX− VOD Figure 7. Differential and Common-Mode Output Voltage Definitions CL 5 pF CL 5 pF 50 Ω 50 Ω Figure 8. Transmitter Test Setup tr tf CLOCK 80% 50% 20% tr tf 2 V 0.8 V DATA 1.4 V Figure 9. TTL Data I/O Valid Levels for AC Measurement |
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