AD9779PCB datasheet(17/34 Pages) AD

17 / 34 page

Preliminary Technical Data

AD9779

Rev. PrD | Page 17 of 34

Data Delay Error

(read only)

Chip

Synchronization

Delay Error (read

only)

Cross Control

Error (read only)

Data Delay Error

Enable

Chip

Synchronization

Error Enable

IRQ Status

Cross Control

Error Enable

7:3

PLL Band Select

See

Table 14 for

values.

11001

PLL Band and Divide

2:0

PLL Ripple Cap

Adjust

111

PLL Enable

0: PLL off, DAC rate clock supplied by outside source

1: PLL on, DAC rate clock synthesized internally from data rate clock via PLL

clock multiplier

6:5

PLL Output Divide

Ratio

00: Divide by 1

01: Divide by 2

10: Divide by 4

11: Divide by 8

4:3

PLL Loop

Feedback Divide

Ratio

00: Divide by 1

01: Divide by 2

10: Divide by 4

11: Divide by 8

PLL Enable and

Charge Pump

Control

2:0

PLL Loop Filter

Bandwidth Tuning

Recommended

Settings. See

Table 14 for PLL

Band Select

values.

000: PLL band select 00000-00111

100: PLL band select 01000-01111

110: PLL band select 10000-10111

111: PLL band select 11000-11111

111

PLL Error Bit

Source

0: Phase error detect

1: Range limit

PLL Reference

Bypass

0: Use PLL reference

1: Use DAC reference

5:3

VCO AGC Gain

Control. See

Table

14 for PLL Band

Select values.

000: PLL band select 00000-00111

100: PLL band select 01000-01111

110: PLL band select 10000-10111

111: PLL band select 11000-11111

111

Misc. Control

2:0

PLL Bias Current

Level/Trim

000

IDAC Gain

7:0

IDAC Gain

Adjustment

(7:0) LSB slice of 10 bit gain setting word for IDAC

11111001

IDAC Sleep

0: IDAC on

1: IDAC off

IDAC Power Down

0: IDAC on

1: IDAC off

IDAC Gain and

Control

1:0

IDAC Gain

Adjustment

(9:8) MSB slice of 10 bit gain setting word for IDAC

Auxiliary DAC1 Gain

7:0

Aux DAC1 Gain

Adjustment

(7:0) LSB slice of 10 bit gain setting word for Aux DAC1

00000000

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