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AM68AX Datasheet(PDF) 1 Page - Texas Instruments |
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AM68AX Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 251 page  AM68Ax Processors, Silicon Revision 1.0 1 Features Processor cores: • Up to dual 64-bit Arm® Cortex®-A72 microprocessor subsystem at up to 2 GHz – 1MB shared L2 cache per dual-core Cortex®- A72 cluster – 32KB L1 D-Cache and 48KB L1 I-Cache per Cortex®-A72 core • Deep Learning Accelerator: – Up to 8 Trillion Operations Per Second (TOPS) • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz in General Compute partition with FFI – 16KB L1 D-Cache, 16KB L1 I-Cache, and 64KB L2 TCM • Dual-core Arm® Cortex®-R5F MCUs at up to 1.0 GHz to support Device Management – 32K L1 D-Cache, 32K I-Cache, and 64K L2 TCM with SECDED ECC on all memories • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators – 480 MPixel/s ISP – Support for up to 16-bit input RAW format – Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support – Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL Multimedia: • Display subsystem supports: – Up to 4 displays – Up to two DSI 4L TX (up to 2.5K) – One eDP 4L – One DPI 24-bit RGB parallel interface – OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface – Safety features such as freeze frame detection and MISR data check • 3D Graphics Processing Unit – IMG BSX-64-4, up to 800 MHz – 50 GFLOPS, 4 GTexels/s – >500 MTexels/s, >8 GFLOPs – Supports at least 2 composition layers – Supports up to 2048x1080 @60fps – Supports ARGB32, RGB565 and YUV formats – 2D graphics capable – OpenGL ES 3.1, Vulkan 1.2 • Two CSI2.0 4L Camera Serial interface (CSI-Rx) Plus CSI2.- 4L Tx (CSI-Tx) with DPHY – MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2 – Support for 1,2,3, or 4 data lane mode up to 1.5Gbps – ECC verification/correction with CRC check + ECC on RAM – Virtual Channel support (up to 16) – Ability to write stream data directly to DDR via DMA • Video Encoder/Decoder – Support for HEVC (H.265) Main profiles at Level 5.1 High-tier – Support for H.264 BaseLine/Main/High Profiles at Level 5.2 – Support for up to 4K UHD resolution (3840 × 2160) – 4K60 H.264/H.265 Encode/Decode (up to 480 MP/s) Memory subsystem: • Up to 4MB of on-chip L3 RAM with ECC and coherency – ECC error protection – Shared coherent cache – Supports internal DMA engine • Up to two External Memory Interface (EMIF) modules with ECC – Supports LPDDR4 memory types – Supports speeds up to 4266 MT/s – Up to two 32-bit data bus with inline ECC up to 17 GB/s per EMIF • General-Purpose Memory Controller (GPMC) • Up to two 512KB on-chip SRAM in MAIN domain, protected by ECC Device security: • Secure boot with secure run-time support • Customer programmable root key, up to RSA-4K or ECC-512 • Embedded hardware security module • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES High speed serial interfaces: • One PCI-Express® (PCIe) Gen3 controllers – Up to four lanes per controller – Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation AM68A SPRSP91 – FEBRUARY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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