AM68AX datasheet(215/251 Pages) TI

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7.10.5.17.2.6 UHS–I DDR50 Mode

Table 7-78 and Figure 7-94 present switching characteristics for MMC1/2 – UHS-I DDR50 Mode.

Table 7-78. MMC1/2 Switching Characteristics – UHS-I DDR50 Mode

see Figure 7-94

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC[x]_CLK

MHz

DDR505

tc(clk)

Cycle time, MMC[x]_CLK

DDR506

tw(clkH)

Pulse duration, MMC[x]_CLK high

9.2

DDR507

tw(clkL)

Pulse duration, MMC[x]_CLK low

9.2

DDR508

td(clkH-cmdV)

Delay time, MMC[x]_CLK rising edge to MMC[x]_CMD transition

1.12

3.46

DDR509

td(clk-dV)

Delay time, MMC[x]_CLK transition to MMC[x]_DAT[3:0] transition

1.12

6.12

x = 1, 2 for MMC1 and MMC2

MMC[x] CLK

MMC[x] CMD

MMC[x] DAT3

[ :0]

DDR508

DDR509

DDR505

DDR506

DDR507

Figure 7-94. MMC1/2 – UHS-I DDR50 – Transmit Mode

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AM68A

SPRSP91 – FEBRUARY 2023

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