74HC4020N datasheet(2/7 Pages) PHILIPS

2 / 7 page

September 1993

Philips Semiconductors

Product speciﬁcation

14-stage binary ripple counter

74HC/HCT4020

FEATURES

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4020 are high-speed Si-gate CMOS

devices and are pin compatible with the “4020” of the

“4000B” series. They are specified in compliance with

JEDEC standard no. 7A.

The 74HC/HCT4020 are 14-stage binary ripple counters

with a clock input (CP), an overriding asynchronous

master reset input (MR) and twelve fully buffered parallel

outputs (Q0, Q3 to Q13).

The counter is advanced on the HIGH-to-LOW transition of

CP.

A HIGH on MR clears all counter stages and forces all

outputs LOW, independent of the state of CP.

Each counter stage is a static toggle flip-flop.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC =5 V

CP to Q0

Qn to Qn+1

66ns

MR to Qn

fmax

maximum clock frequency

101

MHz

input capacitance

3.5

CPD

power dissipation capacitance per package

notes 1 and 2

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