74HCT4024 datasheet(2/7 Pages) PHILIPS

2 / 7 page

December 1990

Philips Semiconductors

Product speciﬁcation

7-stage binary ripple counter

74HC/HCT4024

FEATURES

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4024 are high-speed Si-gate CMOS

devices and are pin compatible with the “4024” of the

“4000B” series. They are specified in compliance with

JEDEC standard no. 7A.

The 74HC/HCT4024 are 7-stage binary ripple counters

with a clock input (CP), an overriding asynchronous

master reset input (MR) and seven fully buffered parallel

outputs (Q0 to Q6).

The counter advances on the HIGH-to-LOW transition of

CP.

A HIGH on MR clears all counter stages and forces all

outputs LOW, independent of the state of CP.

Each counter stage is a static toggle flip-flop.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

APPLICATIONS

• Frequency dividing circuits

• Time delay circuits

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay CP to Q0

CL = 15 pF; VCC = 5 V

fmax

maximum clock frequency

MHz

input capacitance

3.5

CPD

power dissipation capacitance per package

notes 1 and 2

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