40430B datasheet(13/24 Pages) XICOR

13 / 24 page

X40430/X40431 – Preliminary Information

Characteristics subject to change without notice.

13 of 24

REV 1.2.3 11/28/00

www.xicor.com

A similar operation called “Set Current Address” where

the device will perform this operation if a stop is issued

instead of the second start shown in Figure 14. The

device will go into standby mode after the stop and all

bus activity will be ignored until a start is detected. This

operation loads the new address into the address

counter. The next Current Address Read operation will

read from the newly loaded address. This operation

could be useful if the master knows the next address it

needs to read, but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current

address read or random address read. The ﬁrst Data

Byte is transmitted as with the other modes; however,

the master now responds with an acknowledge, indicat-

ing it requires additional data. The device continues to

output data for each acknowledge received. The master

terminates the read operation by not responding with an

acknowledge and then issuing a stop condition.

The data output is sequential, with the data from

address n followed by the data from address n + 1. The

address counter for read operations increments through

all page and column addresses, allowing the entire

memory contents to be serially read during one opera-

tion. At the end of the address space the counter “rolls

over” to address 0000h and the device continues to out-

put data for each acknowledge received. See Figure 16

for the acknowledge and data transfer sequence.

SERIAL DEVICE ADDRESSING

Slave Address Byte

Following a start condition, the master must output a

Slave Address Byte. This byte consists of several parts:

– a device type identiﬁer that is always ‘1010’.

– two bits that provide the device select bits.

– one bit that becomes the MSB of the address.

Figure 14. Current Address Read Sequence

Figure 15. Random Address Read Sequence

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Slave

Address

Byte

Address

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

– one bit of the slave command byte is a R/W bit. The

R/W bit of the Slave Address Byte deﬁnes the opera-

tion to be performed. When the R/W bit is a one, then

a read operation is selected. A zero selects a write

operation.

– After loading the entire Slave Address Byte from the

SDA bus, the device compares the device select bits

with the status of the Device Select pins. Upon a cor-

rect compare, the device outputs an acknowledge on

the SDA line.

40430B Datasheet(PDF) 13 Page - Xicor Inc.

40430B Datasheet(HTML) 13 Page - Xicor Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL