74HC4059D datasheet(4/20 Pages) PHILIPS

4 / 20 page

1998 Jul 08

Philips Semiconductors

Product speciﬁcation

Programmable divide-by-n counter

74HC/HCT4059

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay CP to Q

CL = 15 pF; VCC = 5 V 1820ns

fmax

maximum clock frequency

MHz

input capacitance

3.5

CPD

power dissipation capacitance per package

notes 1 and 2

TYPE

NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

74HC4059N3;

74HCT4059N3

DIP24

plastic dual in-line package; 24 leads (300 mil)

SOT222-1

74HC4059N;

74HCT4059N

DIP24

plastic dual in-line package; 24 leads (600 mil)

SOT101-1

74HC4059D;

74HCT4059D

SO24

plastic small outline package; 24 leads; body width 7.5 mm

SOT137-1

74HC4059D Datasheet(PDF) 4 Page - NXP Semiconductors

74HC4059D Datasheet(HTML) 4 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL