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LT3434

3434f

APPLICATIO S I FOR ATIO

Figure 9. Power Good

VOUT

500mV/DIV

100k TO VIN

VCT

500mV/DIV

VSHDN

2V/DIV

TIME (10ms/DIV)

3434 F09

VIN

PGFB

LT3434

PG at 80% VOUT with 100ms Delay

0.27µF

COUT

200k

VOUT = 3.3V

153k

12k

100k

VIN

PGFB

LT3434

VOUT Disconnect at 80% VOUT

with 100ms Delay

0.27µF

200k

VOUT = 3.3V

153k

12k

100k

VIN

PGFB

LT3434

PG at VIN > 4V with 100ms Delay

0.27µF

VOUT = 3.3V

200k

511k

200k

100k

165k

VIN

PGFB

LT3434

VOUT Disconnect 3.3V Logic Signal

with 100µs Delay

270pF

200k

VOUT = 12V

3434 F10

866k

100k

COUT

Figure 10. Power Good Circuits

LAYOUT CONSIDERATIONS

As with all high frequency switchers, when considering

layout, care must be taken in order to achieve optimal

electrical, thermal and noise performance. For maximum

efficiency switch rise and fall times are typically in the

nanosecond range. To prevent noise both radiated and

conducted the high speed switching current path, shown

in Figure 11, must be kept as short as possible. This is

implemented in the suggested layout of Figure 12. Short-

ening this path will also reduce the parasitic trace induc-

tance of approximately 25nH/inch. At switch off, this

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