74HC4094N datasheet(2/10 Pages) PHILIPS

2 / 10 page

December 1990

Philips Semiconductors

Product speciﬁcation

8-stage shift-and-store bus register

74HC/HCT4094

FEATURES

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4094 are high-speed Si-gate CMOS

devices and are pin compatible with the “4094” of the

“4000B” series. They are specified in compliance with

JEDEC standard no. 7A.

The 74HC/HCT4094 are 8-stage serial shift registers

having a storage latch associated with each stage for

strobing data from the serial input (D) to the parallel

buffered 3-state outputs (QP0 to QP7). The parallel outputs

may be connected directly to common bus lines.

Data is shifted on the positive-going clock (CP) transitions.

The data in each shift register stage is transferred to the

storage register when the strobe input (STR) is HIGH.

Data in the storage register appears at the outputs

whenever the output enable input (OE) signal is HIGH.

Two serial outputs (QS1 and QS2) are available for

cascading a number of “4094” devices. Data is available at

QS1 on the positive-going clock edges to allow high-speed

operation in cascaded systems in which the clock rise time

is fast. The same serial information is available at QS2 on

the next negative-going clock edge and is for cascading

“4094” devices when the clock rise time is slow.

APPLICATIONS

• Serial-to-parallel data conversion

• Remote control holding register

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC = 5 V

CP to QS1

CP to QS2

CP to QPn

STR to QPn

fmax

maximum clock frequency

MHz

input capacitance

3.5

CPD

power dissipation capacitance per package

notes 1 and 2

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