GC4114 datasheet(21/45 Pages) TI

21 / 45 page

Texas Instruments Inc.

- 17 -

MAY 22, 2000

GC4114 QUAD TRANSMIT CHIP

DATA SHEET REV 1.0

This document contains information which may be changed at any time without notice

5.4

INTERPOLATION REGISTERS

Registers 3, and 4 contain the 14 bit interpolation ratio control.

ADDRESS 3:

Interpolation Byte 0

, suggested default = 0x07

BIT

TYPE

NAME

DESCRIPTION

0-7

R/W

INT[0:7]

The LSBs of the interpolation control

ADDRESS 4:

Interpolation Byte 1

, suggested default = 0x00

BIT

TYPE

NAME

DESCRIPTION

0-5

R/W

INT[8:13]

The 6 MSBs of the interpolation control

6,7

zero

Reads back zeros.

Where INT is equal to N-1. The chip interpolates the input data by a factor of 2N for real input data and 4N

for complex input data, where N ranges from 8 to 16384. This provides an interpolation range from 32 to 65,536 for

complex input signals and 16 to 32,768 for real input signals. NOTE: The chip needs to be flushed each time the

interpolation registers are changed. See Section 5.8.

5.5

INPUT MODE REGISTER

This register controls the input bit serial format.

ADDRESS 5:

Input Mode Register

, suggested default = 0x00

BIT

TYPE

NAME

DESCRIPTION

0 LSB

R/W

PACKED

Puts the serial inputs into the 32 bit transfer mode where each complex pair is packed

into 32 bit words. The complex pair is formatted as I word in the upper 16 bits and the

Q word in the lower 16 bits. Each word is formatted as MSB first.

R/W

REAL_INPUT

The serial input accepts real data samples (not complex) when this bit is set. In this

mode a single 16 bit word is expected after every REQ strobe, not a complex pair. The

user has the option to enter real input samples as complex pairs and to not use the

real input mode. If the complex mode (REAL_INPUT = 0) is used to enter real words,

then the real samples should be alternately placed in the I and Q halves of the

complex input pairs. NOTE: the REAL control bit in the interpolation mode register still

needs set to enable real data up conversion.

R/W

SCK_POL

The SIN Input bits and SFS frame strobes are clocked in on the trailing edge of SCK

when this bit is set. The rising edge is used when this bit is low.

R/W

SFS_POL

The SFS signal is treated as active low when this bit is set. Otherwise the signal is

treated as active high.

R/W

PARALLEL_A

The parallel/Serial control for channel A.

R/W

PARALLEL_B

The parallel/Serial control for channel B.

R/W

PARALLEL_C

The parallel/Serial control for channel C.

R/W

PARALLEL_D

The parallel/Serial control for channel D.

The parallel/serial control is low for serial input and high for parallel input. See Section 5.12.

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