74HC595DB datasheet(2/28 Pages) PHILIPS

2 / 28 page

2003 Jun 25

Philips Semiconductors

Product speciﬁcation

8-bit serial-in, serial or parallel-out shift

74HC595; 74HCT595

FEATURES

• 8-bit serial input

• 8-bit serial or parallel output

• Storage register with 3-state outputs

• Shift register with direct clear

• 100 MHz (typical) shift out frequency

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

APPLICATIONS

• Serial-to-parallel data conversion

• Remote control holding register.

DESCRIPTION

The 74HC/HCT595 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT595 is an 8-stage serial shift register with a

storage register and 3-state outputs. The shift register and

storage register have separate clocks.

Data is shifted on the positive-going transitions of the

SH_CP input. The data in each register is transferred to

the storage register on a positive-going transition of the

ST_CP input. If both clocks are connected together, the

shift register will always be one clock pulse ahead of the

storage register.

The shift register has a serial input (DS) and a serial

standard output (Q7’) for cascading. It is also provided

with asynchronous reset (active LOW) for all 8 shift

bus driver outputs. Data in the storage register appears at

the output whenever the output enable input (OE) is LOW.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL × VCC2 × fo) = sum of the outputs.

2. For 74HC595 the condition is VI = GND to VCC.

For 74HCT595 the condition is VI = GND to VCC − 1.5 V.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

74HC

74HCT

tPHL/tPLH

propagation delay

CL = 50 pF; VCC = 4.5 V

SH_CP to Q7’

SH_CP to Qn

MR to Q7’

100

fmax

maximum clock frequency SH_CP and ST_CP

100

MHz

input capacitance

3.5

CPD

power dissipation capacitance per package

notes 1 and 2

115

130

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