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74HC74 Datasheet(PDF) 12 Page - NXP Semiconductors |
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74HC74 Datasheet(HTML) 12 Page - NXP Semiconductors |
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12 / 22 page ![]() 2003 Jul 10 12 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC74; 74HCT74 Family 74HCT GND = 0 V; tr =tf = 6 ns; CL =50pF. SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT WAVEFORMS VCC (V) Tamb = −40 to +85 °C tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.7 4.5 − 18 44 ns propagation delay nSD to nQ, nQ see Fig.8 4.5 − 23 50 ns propagation delay nRD to nQ, nQ see Fig.8 4.5 − 24 50 ns tTHL/tTLH output transition time see Fig.7 4.5 − 719 ns tW clock pulse width HIGH or LOW see Fig.7 4.5 23 9 − ns set or reset pulse width LOW see Fig.8 4.5 20 9 − ns trem removal time set or reset see Fig.8 4.5 8 1 − ns tsu set-up time nD to nCP see Fig.7 4.5 15 5 − ns th hold time nCP to nD see Fig.7 4.5 +3 −3 − ns fmax maximum clock pulse frequency see Fig.7 4.5 22 54 − MHz Tamb = −40 to +125 °C tPHL/tPLH propagation delay nCP to nQ, nQ see Fig.7 4.5 −− 53 ns propagation delay nSD to nQ, nQ see Fig.8 4.5 −− 60 ns propagation delay nRD to nQ, nQ see Fig.8 4.5 −− 60 ns tTHL/tTLH output transition time see Fig.7 4.5 −− 22 ns tW clock pulse width HIGH or LOW see Fig.7 4.5 27 −− ns set or reset pulse width LOW see Fig.8 4.5 24 −− ns trem removal time set or reset see Fig.8 4.5 9 −− ns tsu set-up time nD to nCP see Fig.7 4.5 18 −− ns th hold time nCP to nD see Fig.7 4.5 3 −− ns fmax maximum clock pulse frequency see Fig.7 4.5 18 −− MHz |
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