2003 Jul 10

13

Philips Semiconductors

Product specification

Dual D-type flip-flop with set and reset;

positive-edge trigger

74HC74; 74HCT74

AC WAVEFORMS

handbook, full pagewidth

MNA422

th

tsu

th

tPHL

tPHL

tW

tPLH

tPLH

tsu

1/fmax

VM

VM

VM

VM

VI

GND

VI

GND

nCP input

nD input

VOH

VOL

nQ output

VOH

VOL

nQ output

Fig.7

The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,

the nCP to nD hold times, the output transition times and the maximum clock pulse frequency.

The shaded areas indicate when the input is permitted to change for predictable output performance.