74HC9323AD datasheet(2/6 Pages) PHILIPS

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Philips Semiconductors

Objective specification

74HC/HCT9323A

Programmable ripple counter with oscillator

(3-State)

1995 Oct 27

FEATURES

• 8-pin space saving package

• Programmable 3-stage ripple counter

• Suitable for over-tone crystal application up to 85MHz

(VCC = 5V"10%)

• 3-State output buffer

• Two internal capacitors

• Recommended operating range for use with third overtone

crystals 3V to 6V

• Oscillator stop function (MR)

• Output capability:

bus driver

³ (15 LSTTL)

• I

CC category: MSI

APPLICATIONS

• Control counters

• Timers

• Frequency dividers

• Time-delay circuits

• CIO (Compact Integrated Oscillator)

• Third-overtone crystal operation

DESCRIPTION

The 74HC/HCT9323A are high-speed Si-gate CMOS devices. They

are specified in compliance with JEDEC standard no. 7A.

The HC/HCT 9323A are oscillators designed for quartz crystal

combined with a programmable 3-State counter, a 3-State output

buffer and an overriding asynchronous master reset (MR). With the

two select inputs S1 and S2 the counter can be switched in the

divide-1, 2, 4 or 8 mode. If left floating the clock is divided by 8. The

oscillator is designed to operate either in the fundamental or third

overtone mode depending on the crystal and external components

applied. On-chip capacitors minimize external component count for

third overtone crystal applications.

The oscillator may be replaced by an external clock signal at input

X1. In this event the other oscillator pin (X2) must be floating. The

counter advances on the negative-going transition of X1. A LOW

level on MR resets the counter, stops the oscillator and sets the

output buffer in the 3-State condition. MR can be left floating since

an internal pull-up resistor will make the MR inactive. In the HCT

version, the MR input and the two mode select pins S1 and S2 are

TTL compatible, but the X1 input has CMOS input switching levels

and may be driven by a TTL output using a pull-up resistor

connected to VCC.

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C, tr = tf = 6ns

SYMBOL

PARAMETER

CONDITIONS

Tamb = 25°C; GND = 0V

TYPICAL

UNIT

HCT

tPLH

tPHL

Propagation delay

X1 to OUT (S1 = S2 = LOW)

CL = 50pF; VCC = 5V

fmax

Maximum clock frequency

150

MHz

Input capacitance except X1 and X2

3.5

CPD

Power dissipation

capacitance per package

NOTES:

CPD is used to determine the dynamic power dissipation (PD in µW):

=(CPD

VCC2

fI) + (CL + VCC2

fO) + (Ipull-up

VCC)

where:

= inputfrequency in MHz..

= output frequency in MHz.

VCC = Supply voltage in V.

= Output load capacitance in pF.

Ipull-up = Pull-up currents in µA.

For HC and HCT an external clock is applied to X1 with:

tr = tf v 6ns, VI is GND to VCC, MR = HIGH.

Ipull-up is the summation of –II (µA) of S1 and S2 inputs at the LOW state.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER NUMBER

DWG NUMBER

8-Pin Plastic SO

°C to +70°C

74HC/HCT9323A D

SOT96-1

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