AD7694

Rev. 0 | Page 15 of 16

SDO

*SDO REMAINS LOW IF FURTHER SCK CLOCKS ARE APPLIED WHILE CNV IS LOW

D15

D14

D13

D1

D0

SCK

1

2

3

14

15

16*

CNV

CONVERSION

ACQUISITION

ACQUISITION

Figure 25. Serial Interface Timing

LAYOUT

The printed circuit board that houses the AD7694 should be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. The pinout of the

AD7694 with all its analog signals on the left side and all its

digital signals on the right side eases this task.

Avoid running digital lines under the device because these

couple noise onto the die, unless a ground plane under the

AD7694 is used as a shield. Fast switching signals, such as CNV

or clocks, should never run near analog signal paths. Crossover

of digital and analog signals should be avoided.

At least one ground plane should be used. It could be common

or split between the digital and analog section. In such a case, it

should be joined underneath the AD7694s.

The AD7694 voltage reference input REF has a dynamic input

impedance and should be decoupled with minimal parasitic

inductances. That is done by placing the reference decoupling

ceramic capacitor close to, and ideally right up against, the REF

and GND pins and by connecting these pins with wide, low

impedance traces.

Finally, the power supply, VDD, of the AD7694 should be

decoupled with a ceramic capacitor, typically 100 nF. This

capacitor should be placed close to the AD7694 and connected

using short and large traces to provide low impedance paths

and reduce the effect of glitches on the power supply lines.

EVALUATING THE AD7694’S PERFORMANCE

Other recommended layouts for the AD7694 are outlined in the

evaluation board for the AD7694 (EVAL-AD7694). The

evaluation board package includes a fully assembled and tested

evaluation board, documentation, and software for controlling

the board from a PC via the EVAL-CONTROL BRD2.