will operate in pass mode, allowing the P

the input voltage. As the input voltage drops, the voltage on

the DXX pins will also drop (V

any of the active Dxx pins reaches a voltage approximately

equal to 175mV, the charge pump will switch to the gain of

3/2. This switch-over ensures that the current through the

LEDs never becomes pinched off due to a lack of headroom

across the current sinks.

Only active Dxx pins will be monitored. For example, if only

BankA is enabled, the LEDs in BankB will not affect the gain

transition point. If both banks are enabled, all diodes will be

monitored, and the gain transition will be based upon the

diode with the highest forward voltage. Diode pins D5A and

D3B can have the diode sensing circuity disabled through

the general purpose register if those drivers are not going to

be used.

BankC (D1C) is not a monitored LED current sink.

RESETPin

The LM27965 has a hardware reset pin (RESET) that allows

the device to be disabled by an external controller without

requiring an I

the RESET pin should be held high (logic ’1’) to prevent an

unwanted reset. When the RESET is driven low (logic ’0’), all

internal control registers reset to the default states and the

part becomes disabled. Please see the Electrical Character-

istics section of the datasheet for required voltage thresh-

olds.

I

DATA VALIDITY

The data on SDIO line must be stable during the HIGH

period of the clock signal (SCL). In other words, state of the

data line can only be changed when CLK is LOW.

A pull-up resistor between VIO and SDIO must be greater

than [ (VIO-V

SDIO. Using a larger pull-up resistor results in lower switch-

ing current with slower edges, while using a smaller pull-up

results in higher switching currents with faster edges.

START AND STOP CONDITIONS

START and STOP conditions classify the beginning and the

end of the I

SDIO signal transitioning from HIGH to LOW while SCL line

is HIGH. A STOP condition is defined as the SDIO transition-

ing from LOW to HIGH while SCL is HIGH. The I

always generates START and STOP conditions. The I

is considered to be busy after a START condition and free

after a STOP condition. During data transmission, the I

master can generate repeated START conditions. First

START and repeated START conditions are equivalent,

function-wise.

TRANSFERING DATA

Every byte put on the SDIO line must be eight bits long, with

the most significant bit (MSB) transferred first. Each byte of

data has to be followed by an acknowledge bit. The acknowl-

edge related clock pulse is generated by the master. The

master releases the SDIO line (HIGH) during the acknowl-

edge clock pulse. The LM27965 pulls down the SDIO line

during the 9th clock pulse, signifying an acknowledge. The

LM27965 generates an acknowledge after each byte is re-

ceived.

After the START condition, the I

address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LM27965

address is 36h. For the eighth bit, a “0” indicates a WRITE

and a “1” indicates a READ. The second byte selects the

register to which the data will be written. The third byte

contains data to write to the selected register.

20155025

FIGURE 1. Data Validity Diagram

20155011

FIGURE 2. Start and Stop Conditions

www.national.com

8