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2

SYSTEM BLOCK DIAGRAM

The Figure 2 gives an overview of the complete processor, showing how ARM720T microcontroller and

their peripherals are interfaced.

Figure 2. Block Diagram

AHB

EFT1..2

RxD[2..1]

TxD[2..1]

ECLK1

TDI

TDO

TMS

TCK

TRST

Test/Emu Port

MISO[0..1]

MOSI[0..1]

ECS1n

AN0

(P1.3-0)

UART1..2

BSPI0..1

DATA

RAM

(4k x 32)

Bridge

A

Master I/F

AHB

ASB

Slave I/F

ARM720 Core

ROM

(1k x 32)

APB I/F

EMI

POWER SUPPLY

AN1

AN2

AN3

DMA

Ctrl

AHB

Master I/F

APB

Bridge

Sync.

Port4

SDRAMC

r

b

i

t

e

r

AHB

CAN

CAN RAM

USB

USB RAM

APB

Bridge

ASync.

OSCIN

OSCOUT

Mid[0..31]

Mia[0..13]

MiCsN[0..3]

RAS

CAS

MiWeN

MiBls[0..3]

Edata[0..15]/DD[0..15]

Eadd[1..3]/DA[0..2]

Eadd[4..21]

Erdn/Diorn

Ewr0n/Diown

Ewr1n

Ecs0n

ICs0n

ICs1n

Iordy

Irq

CANRX

CANTX

SCK[0..1]

MiClk

MiClkEn

ATAPI

S-APB

GPIO

WDG

EIC

APB I/F

RCCU

GPIO

APB I/F

RTC

APB I/F

32 kHz

OSC

ADC

Port1

USBCK

WIU

APB I/F

EXT_BOOT

EINT0

EINT1

EINT2

EINT3

EINT4

GPIO

APB I/F

Port3

STOP_REQ

ESAI

APB I/F

ADAC

APB I/F

OUTPR

OUTPL

(P1.4-7)

SCK

STD0

SC0

SC1

SC2

SRD

Eready