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LTC4011

4011p

APPLICATIO S I FOR ATIO

that programs the correct number of series cells when it

is connected to the charger, along with indicating chem-

istry and providing temperature information.

Any of these battery pack charge control concepts could

be combined in a variety of ways to service custom

application needs.

1. Input capacitors should be placed as close as possible

to switching FET supply and ground connections with

the shortest copper traces possible. The switching

FETs must be on the same layer of copper as the input

capacitors. Vias should not be used to make these

connections.

2. Place the LTC4011 close to the switching FET gate

terminals, keeping the connecting traces short to

produce clean drive signals. This rule also applies to

IC supply and ground pins that connect to the switch-

ing FET source pins. The IC can be placed on the

opposite side of the PCB from the switching FETs.

3. Place the inductor input as close as possible to the

drain of the switching FETs. Minimize the surface area

of the switch node. Make the trace width the minimum

needed to support the programmed charge current.

Use no copper fills or pours. Avoid running the con-

nection on multiple copper layers in parallel. Minimize

capacitance from the switch node to any other trace or

plane.

4. Place the charge current sense resistor immediately

adjacent to the inductor output, and orient it such that

current sense traces to the LTC4011 are short. These

feedback traces need to be run together as a single pair

with the smallest spacing possible on any given layer

on which they are routed. Locate any filter component

on these traces next to the LTC4011, and not at the

sense resistor location.

5. Place output capacitors adjacent to the sense resisitor

output and ground.

6. Output capacitor ground connections must feed into

the same copper that connects to the input capacitor

ground before tying back into system ground.

Figure 12. NiMH Battery Pack Indicating Number of Cells

Figure 13. High Speed Switching Path

PCB Layout Considerations

To prevent magnetic and electrical field radiation and high

frequency resonant problems, proper layout of the com-

ponents connected to the LTC4011 is essential. Refer to

Figure 13. For maximum efficiency, the switch node rise

and fall times should be minimized. The following PCB

design priority list will help ensure proper topology. Lay-

out the PCB using this specific order.

1500mAhr

NiMH CELLS

BATTERY

PACK

VTEMP

VCELL

CHEM

4011 F12

–

10k

NTC

4011 F13

VBAT

VIN

HIGH

FREQUENCY

CIRCULATING

PATH

BAT

SWITCH NODE

CIN

SWITCHING GROUND

COUT

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