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74LVC2952APW Datasheet(PDF) 2 Page - NXP Semiconductors

Part # 74LVC2952APW
Description  Octal registered tranceiver with 5-volt tolerant inputs/ouputs 3-State
PDF  11 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC2952APW Datasheet(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LVC2952A
Octal registered tranceiver with 5-volt tolerant
inputs/ouputs (3-State)
2
1998 Jul 29
853-1993 19803
FEATURES
• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
• Wide supply voltage range of 1.2 V to 3.6 V
• In accordance with the JEDEC standard no. 8-1 A
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Flow-through pin-out architecture
• 3-State outputs
• Direct interface with TTL levels
• Integrated 30W damping resistor
DESCRIPTION
The 74LVC2952A is a low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families. The
74LVC2952A is an octal non-inverting registered transceiver. Two 8-bit
back to back registers store data flowing in both directions between two
bidirectional busses. Data applied to the inputs is entered and stored on
the rising edge of the clock (CPnn) provided that the clock enable CEnn)
is LOW. The data is then present at the 3-State output buffers, but is
only accessible when the output enable input (OEnn) is LOW. Data flow
from A inputs to B outputs is the same as for B inputs to A outputs. The
74LVC2952A is identical to the 74LVC2953A but has non-inverting
outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
CPnn to An, Bn
CL = 50 pF;
VCC = 3.3 V
4.3
ns
fmax
Maximum clock frequency
150
MHz
CI
Input capacitance
5
pF
CI/O
Input/output capacitance
10
pF
CPD
Power dissipation capacitance per buffer
VCC = 3.3V1
31
pF
NOTE:
1CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic SO
–40
°C to +125°C
74LVC2952A D
74LVC2952A D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°C to +125°C
74LVC2952A DB
74LVC2952A DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LVC2952A PW
74LVC2952APW DH
SOT355-1
PIN CONFIGURATION
SV01716
B7
B6
B5
B4
B3
B2
B1
B0
OEAB
CPAB
CEAB
CEBA
CPBA
OEBA
1
2
3
4
5
6
7
8
9
10
11
12
GND
VCC
A7
A6
A5
A4
A3
A2
A1
A0
24
23
22
21
20
19
18
17
16
15
14
13
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
8, 7, 6, 5, 4, 3, 2, 1,
B0 to B7
B data inputs/outputs
12
GND
Ground (0 V)
9, 15
OEAB,OEBA
Output enable inputs
(active LOW)
10, 14
CPAB, CPBA
Clock inputs
11, 13,
CEAB, CEBA
Clock enable inputs
16, 17, 18, 19, 20,
21, 22, 23
A0 to A7
A data inputs/outputs
24
VCC
Positive supply voltage



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