Philips Semiconductors

Product specification

74LVC377

Octal D-type flip-flop with data enable;

positive-edge trigger

1998 Jul 29

5

AC CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

WAVEFORM

UNIT

MIN

MAX

MIN

TYP

MAX

Propagation delay

CP to Qn

1

6.0

10.2

6.6

11.2

ns

Clock pulse width

HIGH or LOW

1

4

1.0

5

1.6

ns

Set-up time

E to CP

2

4

2.3

5

2.9

ns

Hold time

E to CP

2

0

–2.2

0

–2.8

ns

Set-up time

3

2

1.3

3

1.8

ns

Hold time

3

0

–1.2

0

–1.6

ns

Maximum clock

pulse frequency

1

125

100

MHz

NOTE:

AC WAVEFORMS

VM

VM

1/fMAX

tw

tPHL

tPLH

CP INPUT

Qn OUTPUT

SW00078

GND

Waveform 1. Clock (CP) to output (Qn) propagation delays the

clock pulse width and the maximum clock pulse frequency.

SY00061

NOTE: The shaded areas indicate when the input is permitted to change

for predictable output performance.

E Input

GND

STABLE

CP Input

GND

GND

Waveform 2. Data set-up and hold times from the data input

(Dn) and from the enable

input (E) to the clock (CP).