Philips Semiconductors

Product specification

74LVC573A

Octal D-type transparent latch with 5-volt

tolerant inputs/outputs (3-State)

1998 Jul 29

4

LOGIC DIAGRAM

LE

Q

D

D0

D

D1

D

D2

D

D3

D

D4

D

D5

D

D6

D

D7

LE

LE

LE LE

LE LE

LE LE

LE LE

LE LE

LE LE

LE LE

QQ

Q

Q

Q

Q

Q

SA00399

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

OE

LATCH

1

LATCH

2

LATCH

3

LATCH

4

LATCH

5

LATCH

6

LATCH

7

LATCH

8

FUNCTION TABLE

OPERATING MODES

INPUTS

INTERNAL LATCHES

OUTPUTS

OPERATING MODES

OE

LE

INTERNAL LATCHES

Enable and read register

(transparent mode)

L

L

H

H

L

H

L

H

L

H

Latch and read register

L

L

L

L

l

h

L

H

L

H

Latch register and

disable outputs

H

H

L

L

l

h

L

H

Z

Z

H = HIGH voltage level

h

= HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition

L

= LOW voltage level

l

= LOW voltage level one setup time prior to the HIGH-to-LOW LE transition

X = Don’t care

Z = High impedance OFF-state