Electronic Components Datasheet Search
  English  ▼

X  

NP3700 Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers

Part # NP3700
Description  5-Gbps Network Processor with Integrated Traffic Manager
PDF  4 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ETC [List of Unclassifed Manufacturers]
Direct Link  
Logo ETC - List of Unclassifed Manufacturers

NP3700 Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers

  NP3700 Datasheet HTML 1Page - List of Unclassifed Manufacturers NP3700 Datasheet HTML 2Page - List of Unclassifed Manufacturers NP3700 Datasheet HTML 3Page - List of Unclassifed Manufacturers NP3700 Datasheet HTML 4Page - List of Unclassifed Manufacturers  
Zoom Inzoom in Zoom Outzoom out
 2 / 4 page
background image
Product Brief
nP3700
5-Gbps Network Processor with Integrated Traffic Manager
PB37xx / V0.92 / 053003
2
Empowering Intelligent Wide Area Networks
nP3700 Family Highlights
Interfaces
• Line Interfaces – cell and packet
• Support for Deep Channelization: for
OC-1s, T3/E3s, T1/E1s, etc.
• Fabric Interface: OIF SPI-4 Phase 2
- 800 MHz
• External Memory Interfaces:
RLDRAM II memory controllers
- Payload Memory – 2 banks of 36-bit
RLDRAM II or DDR SDRAM
operating at up to 250 MHz
(32 Gbps with ECC)
- Context Memory:
2 banks of 36-bit RLDRAM II or
DDR SRAM operating at up to
250 MHz (32 Gbps with ECC)
- Channel Service Memory:
One bank of 36-bit QDR-II SRAM
operating at up to 250 MHz
- Flow Database Memory:
Two banks of 18-bit QDR-II SRAM
operating at up to 250 MHz
• CPU Interfaces: PowerPC and
Gigabit Ethernet
• External Search Interface
- Compliant with NPF
- Backward compatibility mode with
existing TCAMs
• Debug port
• JTAG port
High Performance nPcores
• 3 nPCores at 700 MHz
Integrated Coprocessors
• Policy Engine for efficient packet
classification
• Special Purpose Unit (SPU) for per-
flow policing
• Hashing Unit
• On-Chip Debugger (OCD)
Integrated Traffic Manager
• Hierarchical Traffic Manager with
fine-grained flow-based traffic
management
• Leverages field-proven nPX5710 and
nPX5720 technology
SPI-3
GE
SPI-4.2
nP3700
2
1
1
nP3700 Block Diagram
SPI3/UT3
SPI3/UT3
SPI4.2
nPcores
3 cores @ 700 MHz
SPU
Packet Transform
Engine
Traffic
Manager
Queuing
&
Scheduling
(Switch
Fabric)
Channel
buffers
Policy
Engine
DRAM
CPU Interface
Debug
JTAG
PPC
36
36
36
36
Cache
Hash
Engine
Scratch
Pad
Memory Access Unit
NPF(QDR)
QDR
DRAM/SRAM
36
36
18
GE
(Line/CPU)
SPI3/UT3
SPI3/UT3
SPI4.2
nPcores
3 cores @ 700 MHz
SPU
Packet Transform
Engine
Traffic
Manager
Queuing
&
Scheduling
(Switch
Fabric)
Channel
buffers
Policy
Engine
DRAM
CPU Interface
Debug
JTAG
PPC
36
36
36
36
Cache
Hash
Engine
Scratch
Pad
Memory Access Unit
NPF(QDR)
QDR
DRAM/SRAM
36
36
18
GE
(Line/CPU)



Html Pages

1 2 3 4


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com