P89V51RB2BBC datasheet(29/80 Pages) NXP

29 / 80 page

P89V51RB2_RC2_RD2_5

Product data sheet

Rev. 05 — 12 November 2009

29 of 80

NXP Semiconductors

P89V51RB2/RC2/RD2

8-bit microcontrollers with 80C51 core

6.4.1 Mode 0

Putting either Timer into mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a ﬁxed divide-by-32 prescaler. Figure 8 shows mode 0 operation.

In this mode, the Timer register is conﬁgured as a 13-bit register. As the count rolls over

from all 1s to all 0s, it sets the Timer interrupt ﬂag TFn. The count input is enabled to the

Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the Timer

to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a

control bit in the Special Function Register TCON (Figure 7). The GATE bit is in the TMOD

The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper

3 bits of TLn are indeterminate and should be ignored. Setting the run ﬂag (TRn) does not

clear the registers.

Mode 0 operation is the same for Timer 0 and Timer 1 (see Figure 8). There are two

different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

6.4.2 Mode 1

Mode 1 is the same as mode 0, except that all 16 bits of the timer register (THn and TLn)

are used. See Figure 9.

IT1

Interrupt 1 Type control bit. Set/cleared by software to specify falling

edge/low level that triggers external interrupt 1.

IE0

Interrupt 0 Edge ﬂag. Set by hardware when external interrupt 0

edge/low level is detected. Cleared by hardware when the interrupt is

processed, or by software.

IT0

Interrupt 0 Type control bit. Set/cleared by software to specify falling

edge/low level that triggers external interrupt 0.

Table 18.

TCON - Timer/counter control register (address 88H) bit description …continued

Bit

Symbol

Description

Fig 8.

Timer/counter 0 or 1 in mode 0 (13-bit counter)

002aaa519

osc/6

Tn pin

TRn

TnGate

INTn pin

C/T = 0

C/T = 1

TLn

(5-bits)

THn

(8-bits)

TFn

control

overflow

interrupt

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