8.3 Feature Description

8.3.1 Integrated Line Filter

The TPSF12C3 has a built-in input line filter. Because the entire filter is integrated in the device, matching is

better than what can be achieved using discrete components. This filter not only removes virtually all input at line

frequency, it also sums the signals from the sense inputs to create a signal that represents the common-mode

noise signature without line-frequency components.

8.3.2 Compensation

The TPSF12C3 contains partial internal compensation that, when combined with two capacitors and a

resistor between COMP1 and COMP2, forms a lead-lag network. This internal network allows fewer external

components to be used.

8.3.3 Enable

The TPSF12C3 has an enable input, EN, that allows the device to be shut down, drastically reducing power

consumption during intervals when EMI mitigation is not required. The typical quiescent current consumption is

12.5 mA and 50 μA when the device is enabled and disabled, respectively. Because many designs do not use

this feature, a 900-kΩ pull up resistor connects internally between VDD and EN, allowing the EN pin to be left

open.

In addition, INJ is pulled low when the device is disabled to reduce the parasitic resistance in series with CINJ.

8.3.4 Supply Voltage UVLO Protection

To ensure that the TPSF12C3 operates safely while VDD is powered on and off as well as during brownout

conditions, this device has a built-in UVLO protection to provide predictable behavior while VDD is below its

operating voltage. UVLO releases when the VDD voltage exceeds 7.95 V, allowing normal operation. UVLO

engages if the VDD voltage falls below approximately 6.6 V. There is approximately 1 V of UVLO hysteresis.

8.3.5 Thermal Shutdown Protection

The TPSF12C3 provides built-in overtemperature protection that shuts down the device if the junction

temperature exceeds approximately 175°C. After junction temperature drops by approximately 20°C, the device

restarts. This process is repeated until the ambient temperature or power dissipation is reduced.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

The EN pin provides ON and OFF control for the TPSF12C3. When the EN voltage is below approximately 0.8

V, the device is in shutdown mode. Most internal circuitry is shutdown. The quiescent current in shutdown mode

drops to 50 µA (typical). The TPSF12C3 also employs VDD internal undervoltage protection. If the VDD voltage

is below its UV threshold, the IC remains off. The INJ output pulls to ground while in shutdown mode.

8.4.2 Active Mode

The TPSF12C3 is in active mode when VVDD is above its UVLO threshold, EN is high, and there is no

overtemperature fault. The simplest way to enable operation is to connect EN to VDD, which allows startup

when the applied supply voltage exceeds the UVLO threshold voltage. In this mode, the device amplifies signals

on COMP2 and outputs the amplified signal on the INJ pin.

TPSF12C3

SNVSCB8 – MARCH 2023

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