ZL30250, ZL30251

Product Brief

2

Microsemi Corporation

1. Application Examples

50MHz

2x 156.25MHz differential

Frequency synthesis from crystal resonator

125MHz CMOS

25MHz CMOS

Figure 2 – Ethernet Frequency Synthesis Application

25MHz

3x 100MHz differential

Frequency multiplication from input clock signal

Figure 3 – PCI Express Frequency Multiplication Application

2. Detailed Features

2.1 Input Clock Features

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Four input clocks: one crystal/CMOS, two differential/CMOS, one single-ended/CMOS

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Input clocks can be any frequency from 9.72MHz up to 1250MHz (differential) or 300MHz (CMOS)

2.2 APLL Features

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Very high-resolution fractional scaling (i.e. non-integer multiplication)

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Any-to-any frequency conversion with 0ppm error

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Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5)

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Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter

components

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Bypass mode supports system testing

2.3 Output Clock Features

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Three low-jitter output clocks

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Each output can be one differential output or two CMOS outputs

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Output clocks can be any frequency from 1Hz to 1035MHz (250MHz max for CMOS and HSTL outputs)

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Output jitter is typically 0.16 to 0.28ps RMS (12kHz to 20MHz integration band)

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In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin

(Example: OC3P 125MHz, OC3N 25MHz)

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Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components

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Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN

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Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components

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Can produce PCIe clocks (PCIe gen. 1, 2 and 3)

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Sophisticated output-to-output phase alignment

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Per-output phase adjustment with high resolution and unlimited range

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Per-output enable/disable

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Per-output glitchless start/stop (stop high or low)

ZL3025x

ZL3025x