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MM58248N Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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MM58248N Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 6 page  Absolute Maximum Ratings If MilitaryAerospace specified devices are required please contact the National Semiconductor Sales OfficeDistributors for availability and specifications Voltage at Any Input Pin VDD a 03V to VSS b 03V Voltage at Any Display Pin VDD to VDD b 625V VDD a lVDISl 625V Storage Temperature b 65 Cto a150 C Power Dissipation at a25 C Molded DIP Package Board Mount 228W Molded DIP Package Socket Mount 205W Molded DIP Package Board Mount iJA e 46 CW Derate 217 mW C above a25 C Molded DIP Package Socket Mount iJA e 51 CW Derate 196 mW C above a25 C Junction Temperature 130 C Lead Temperature (Soldering 10 seconds) 260 C Operating Conditions Min Max Units Supply Voltage (VDD) VSS e 0V 45 55 V Display Voltage (VDIS) b 55 b 25 V Temperature Range b 40 a 85 C DC Electrical Characteristics TA eb40 Cto a85 C VDD e 5V g05V VSS e 0V unless otherwise specified Symbol Parameter Conditions Min Typ Max Units IDD Power Supply Currents VIN e VSS or VDD VSS e 0V 150 m A VDIS Disconnected IDIS VDD e 55V VSS e 0V 10 mA VDIS eb55V All Outputs Low VIL Input Logic Levels 08 V DATA IN CLOCK Logic ‘0’ VIH Input Logic Levels (Note 1) 24 V DATA IN CLOCK Logic ‘1’ IIN Input Currents DATA IN CLOCK VIN e 0V or VDD b 10 10 m A CIN Input Capacitance DATA IN CLOCK 15 pF ROFF Display Output Impedances VDD e 55V VSS e 0V Output Off (Figure 3a) VDIS eb25V 60 400 kX VDIS eb40V 70 550 kX VDIS eb55V 80 650 kX RON Display Output Impedances VDD e 55V VSS e 0V Output on (Figure 3b) VDIS eb25V 30 40 kX VDIS eb40V 26 37 kX VDIS eb55V 23 34 kX VDOL Display Output VDD e 55V IOUT e Open Circuit VDIS VDIS a 4V Low Voltage b 55V s VDIS s b25V Note 1 74LSTTL VOH e 27V IOUT eb400 mA TTL VOH e 24V IOUT eb400 mA AC Electrical Characteristics TA eb40 Cto a85 C VDD e 5V g05V Symbol Parameter Conditions Min Typ Max Units fC Clock Input Frequency (Notes 2 3) 10 MHz tH Clock Input High Time 300 ns tL Clock Input Low Time 300 ns tDS Data Input Setup Time CL e 50 pF 100 ns tDH Data Input Hold Time 100 ns Note 2 AC input waveform specification for test purposes tr tf s 20 ns f e 1 MHz 50% g10% duty cycle Note 3 Clock input rise and fall times must not exceed 5 ms 2 |
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