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STM8AF6346TA Datasheet(PDF) 44 Page - STMicroelectronics

Part # STM8AF6346TA
Description  Automotive 8-bit MCU, with up to 32-Kbyte Flash memory, data EEPROM, 10-bit ADC, timers, LIN, SPI, I2C, 3 to 5.5 V
PDF  95 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM8AF6346TA Datasheet(HTML) 44 Page - STMicroelectronics

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Option bytes
STM8AF6366
44/95
DS12343 Rev 2
9
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Each option
byte has to be stored twice, for redundancy, in a regular form (OPTx) and a complemented
one (NOPTx), except for the ROP (read-out protection) option byte and option bytes 8 to 16.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 15: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP and UBC options that can only be toggled in ICP mode (via SWIM).
Refer to the STM8 Flash programming manual (PM0051) and STM8 SWIM communication
protocol and debug module user manual (UM0470) for information on SWIM programming
procedures.
Table 15. Option bytes
Addr.
Option
name
Option
byte no.
Option bits
Factory
default
setting
76
5
4
3
2
1
0
0x00
4800
Read-out
protection
(ROP)
OPT0
ROP[7:0]
0x00
0x00
4801
User boot
code
(UBC)
OPT1
Reserved
UBC[5:0]
0x00
0x00
4802
NOPT1
Reserved
NUBC[5:0]
0xFF
0x00
4803
Alternate
function
remapping
(AFR)
OPT2
AFR7
AFR6
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
0x00
0x00
4804
NOPT2
NAFR
7
NAFR
6
NAFR
5
NAFR
4
NAFR
3
NAFR
2
NAFR
1
NAFR
0
0xFF
0x00
4805
Watchdog
option
OPT3
Reserved
HSITRI
M
LSI
_EN
IWDG
_HW
WWDG
_HW
WWDG
_HALT
0x00
0x00
4806
NOPT3
Reserved
NHSITRI
M
NLSI
_EN
NIWDG
_HW
NWWD
G_HW
NWWG
_HALT
0xFF
0x00
4807
Clock
option
OPT4
Reserved
EXT
CLK
CKAWU
SEL
PRS
C1
PRS
C0
0x00
0x00
4808
NOPT4
Reserved
NEXT
CLK
NCKAW
USEL
NPR
SC1
NPR
SC0
0xFF
0x00
4809
HSE clock
startup
OPT5
HSECNT[7:0]
0x00
0x00
480A
NOPT5
NHSECNT[7:0]
0xFF



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