FN4000 Rev 0.00

Page 1 of 10

April 1995

FN4000

Rev 0.00

April 1995

ACTS373MS

Radiation Hardened Octal Transparent Latch, Three-State

DATASHEET

NOT RECOMMENDED FOR NEW DESIGNS

NO RECOMMENDED REPLACEMENT

contact our Technical Support Center at

1-888-INTERSIL or www.intersil.com/tsc

Features

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose 300K RAD (Si)

• Single Event Upset (SEU) Immunity

<1 x 10-10 Errors/Bit-Day (Typ)

• SEU LET Threshold >80 MEV-cm2/mg

• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range: -55oC to +125oC

• Significant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

- VIL = 0.8V Max

- VIH = VCC/2V Min

• Input Current

1A at VOL, VOH

Description

The Intersil ACTS373MS is a radiation hardened octal trans-

parent latch with three-state outputs. The outputs are transpar-

ent to the inputs when the latch enable (LE) is high. When the

LE goes low, the data is latched. When the Output Enable (OE)

is high, the outputs are in the high impedance state. The latch

operation is independent of the state of the output enable.

The ACTS373MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of the

radiation hardened, high-speed, CMOS/SOS Logic Family.

Pinouts

20 LEAD CERAMIC DUAL-IN-LINE

MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C

TOP VIEW

20 LEAD CERAMIC FLATPACK

MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C

TOP VIEW

Ordering Information

Truth Table

11

12

13

14

15

16

17

18

20

19

10

9

8

7

6

5

4

3

2

1

OE

Q0

D0

D1

Q1

Q2

D3

D2

Q3

GND

VCC

D7

D6

Q6

Q7

Q5

D5

D4

Q4

LE

2

3

4

5

6

7

8

120

19

18

17

16

15

14

13

OE

Q0

D0

D1

Q1

Q2

D2

D3

9

10

12

11

Q3

GND

VCC

Q7

D7

D6

Q6

Q5

D5

D4

Q4

LE

PART NUMBER

TEMPERATURE RANGE

SCREENING LEVEL

PACKAGE

ACTS373DMSR

-55oC to +125oC

Intersil Class S Equivalent

20 Lead SBDIP

ACTS373KMSR

-55oC to +125oC

Intersil Class S Equivalent

20 Lead Ceramic Flatpack

ACTS373D/Sample

+25oC

Sample

20 Lead SBDIP

ACTS373K/Sample

+25oC

Sample

20 Lead Ceramic Flatpack

ACTS373HMSR

+25oCDie

Die

OE

LE

DQ

Functional Diagram

LH

H

H

LHL

L

LL

I

L

LLh

H

HX

X

Z

NOTE:

L = Low Voltage Level

H = High Voltage Level

X = Don’t Care

Z = High Impedance State

I = Low voltage level one set-up time prior to the high to low latch enable transition

h = High voltage level one set-up time prior to the high to low latch enable transition

DQ

LE

D

LE

Q

OE

LATCH

COMMON

OE

1 OF 8

(3, 4, 7, 8, 13,

14, 17, 18)

(2, 5, 6, 9, 12,

15, 16, 19)

(1)

(11)

CONTROLS