AT25SF321B datasheet(28/63 Pages) RENESAS

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DS-AT25SF321B-179 Rev. F

Page 28

2022-06-03

AT25SF321B Datasheet

8.3

Block Erase (20h, 52h, or D8h)

A block of 4, 32, or 64 kbytes can be erased (all bits set to the logical 1 state) in a single operation by using one of

three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-kbytes erase, an opcode

of 52h is used for a 32-kbytes erase, and D8h is used for a 64-kbytes erase. Before a Block Erase command can

be started, the Write Enable command must have been previously issued to the device to set the WEL bit of the

Status Register to a logical 1 state.

To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must

be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address

within the 4- or 32- or 64-kbytes block to be erased must be clocked in. Any additional data clocked into the device

is ignored. When the CS pin is deasserted, the device erases the appropriate block. The erasing of the block is

internally self-timed and takes place in a time of tBLKE.

Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded

by the device. Therefore, for a 4-kbytes erase, address bits A11-A0 are ignored by the device, and their values

can be either a logical 1 or 0. For a 32-kbytes erase, address bits A14-A0 are ignored by the device. For a 64-

kbytes erase, address bits A15-A0 are ignored by the device. Despite the lower-order address bits not being

decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is

deasserted, and the CS pin must be deasserted on a byte boundary (multiples of eight bits); otherwise, the device

aborts the operation, and no erase operation is performed.

If the memory is in the protected state, the Block Erase command is not executed, and the device returns to the

idle state once the CS pin has been deasserted.

The WEL bit in the Status Register is reset to the logical 0 state if: the erase cycle aborts due to an incomplete

address being sent, the CS pin is deasserted on uneven byte boundaries, or because a memory location within

the region to be erased is protected.

While the device is executing a successful erase cycle, the Status Register can be read and indicates that the

device is busy. For faster throughput, it is recommended that the Status Register be polled to determine if the

device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register is

reset to the logical 0 state.

Figure 20. Block Erase Timing

SCK

MSB

CCCCCCCC

410 11

812

29 30

27 28

OPCODE

AAAA

AAA

ADDRESS BITS A23-A0

HIGH-IMPEDANCE

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