©2019 Integrated Device Technology, Inc.

1

JUNE 2019

DSC-4852/8

I/O

Control

Address

Decoder

128Kx8

MEMORY

ARRAY

70V09

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE 0L

OEL

R/

WL

A16L

A0L

I/O 0-7L

SEML

INTL

(2)

BUSYL

(1,2)

R/

W L

CE0L

OEL

I/O

Control

Address

Decoder

OER

R/

WR

CE0R

A16R

A 0R

I/O 0-7R

SEMR

INT R

(2)

R

BUSY

(1,2)

M/

S

(1)

CE1L

R/

WR

CE0R

OER

CE1R

4852 drw 01

1L

CE

1R

CE

17

17

Functional Block Diagram

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M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

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Busy and Interrupt Flags

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On-chip port arbitration logic

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Full on-chip hardware support of semaphore signaling

between ports

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Fully asynchronous operation from either port

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LVTTL-compatible, single 3.3V (±0.3V) power supply

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Available in a 100-pin TQFP

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Industrial temperature range (–40°C to +85°C) is available

for selected speeds

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Green parts available, see ordering information

Features

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True Dual-Ported memory cells which allow simultaneous

access of the same memory location

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High-speed access

– Commercial: 15ns (max.)

– Industrial: 20ns (max.)

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Low-power operation

– IDT70V09L

Active: 440mW (typ.)

Standby: 660µW (typ.)

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Dual chip enables allow for depth expansion without

external logic

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IDT70V09 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading more

than one device

HIGH-SPEED 3.3V

128K x 8 DUAL-PORT

STATIC RAM

70V09L

NOTES:

1. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).