6.42

70V37L

High-Speed 3.3V 32K x 18 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

13

Truth Table IV — Interrupt Flag(1,4,5)

Waveform of Interrupt Timing(1,5)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. Refer to Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

5. Refer to Truth Table I - Chip Enable.

NOTES:

1. Assumes BUSYL = BUSYR =VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTL and INTR must be initialized at power-up.

5. Refer to Truth Table I - Chip Enable.

4851 drw 15

ADDR"A"

INTERRUPT SET ADDRESS

CE"A"

R/

W"A"

tAS

tWC

tWR

(3)

(4)

tINS

(3)

INT"B"

(2)

4851 drw 16

ADDR"B"

INTERRUPT CLEAR ADDRESS

CE"B"

OE"B"

tAS

tRC

(3)

tINR

(3)

INT"B"

(2)

Left Port

Right Port

Function

R/WL

CEL

OEL

A14L-A0L

INTL

R/WR

CER

OER

A14R-A0R

INTR

L

L

X

7FFF

XX

XX

X

L(2)

Set Right INTR Flag

X

X

X

X

X

X

L

L

7FFF

H(3)

Reset Right INTR Flag

XX

X

X

L(3)

L

L

X

7FFE

X

Set Left INTL Flag

XL

L

7FFE

H(2)

X

X

X

X

X

Reset Left INTL Flag

4851 tbl 16