74F646 datasheet(3/12 Pages) NSC

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Unit LoadingFan Out

54F74F

Pin Names

Description

Input IIH IIL

HIGHLOW

Output IOH IOL

A0–A7

Data Register A Inputs

351083

70 mA b650 mA

TRI-STATE Outputs

6001066 (80) b12 mA64 mA (48 mA)

B0–B7

Data Register B Inputs

351083

70 mA b650 mA

TRI-STATE Outputs

6001066 (80) b12 mA64 mA (48 mA)

CPAB CPBA Clock Pulse Inputs

1010

20 mA b06 mA

SAB SBA

Select Inputs

1010

20 mA b06 mA

Output Enable Input

1010

20 mA b06 mA

DIR

Direction Control Input

1010

20 mA b06 mA

Function Table

Inputs

Data IO

Function

DIR

CPAB

CPBA

SAB

SBA

A0–A7

B0–B7

H or L

Isolation

Input

Clock An Data into A Register

Clock Bn Data into B Register

An to Bn Real Time (Transparent Mode)

Input

Output

Clock An Data into A Register

H or L

A Register to Bn (Stored Mode)

Clock An Data into A Register and Output to Bn

Bn to An Real Time (Transparent Mode)

Output

Input

Clock Bn Data into B Register

H or L

B Register to An (Stored Mode)

Clock Bn Data into B Register and Output to An

The data output functions may be enabled or disabled by various signals at the G and DIR Inputs Data input functions are always enabled ie data at the bus

pins will be stored on every LOW-to-HIGH transition of the clock inputs

H e HIGH Voltage Level

L e LOW Voltage Level

X e Irrelevant

L e LOW-to-HIGH Transition

74F646 Datasheet(PDF) 3 Page - National Semiconductor (TI)

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