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80C31 Datasheet(PDF) 23 Page - NXP Semiconductors |
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80C31 Datasheet(HTML) 23 Page - NXP Semiconductors |
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23 / 38 page  Philips Semiconductors Product specification 80C51/87C51/80C31 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V), low power, high speed (33 MHz) 2000 Jan 20 23 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = +2.7V to +5.5V, VSS = 0V1, 2, 3 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 14 Oscillator frequency5 Speed versions :S 3.5 16 MHz tLHLL 14 ALE pulse width 85 2tCLCL–40 ns tAVLL 14 Address valid to ALE low 22 tCLCL–40 ns tLLAX 14 Address hold after ALE low 32 tCLCL–30 ns tLLIV 14 ALE low to valid instruction in 150 4tCLCL–100 ns tLLPL 14 ALE low to PSEN low 32 tCLCL–30 ns tPLPH 14 PSEN pulse width 142 3tCLCL–45 ns tPLIV 14 PSEN low to valid instruction in 82 3tCLCL–105 ns tPXIX 14 Input instruction hold after PSEN 0 0 ns tPXIZ 14 Input instruction float after PSEN 37 tCLCL–25 ns tAVIV 4 14 Address to valid instruction in 207 5tCLCL–105 ns tPLAZ 14 PSEN low to address float 10 10 ns Data Memory tRLRH 15, 16 RD pulse width 275 6tCLCL–100 ns tWLWH 15, 16 WR pulse width 275 6tCLCL–100 ns tRLDV 15, 16 RD low to valid data in 147 5tCLCL–165 ns tRHDX 15, 16 Data hold after RD 0 0 ns tRHDZ 15, 16 Data float after RD 65 2tCLCL–60 ns tLLDV 15, 16 ALE low to valid data in 350 8tCLCL–150 ns tAVDV 15, 16 Address to valid data in 397 9tCLCL–165 ns tLLWL 15, 16 ALE low to RD or WR low 137 239 3tCLCL–50 3tCLCL+50 ns tAVWL 15, 16 Address valid to WR low or RD low 122 4tCLCL–130 ns tQVWX 15, 16 Data valid to WR transition 13 tCLCL–50 ns tWHQX 15, 16 Data hold after WR 13 tCLCL–50 ns tQVWH 16 Data valid to WR high 287 7tCLCL–150 ns tRLAZ 15, 16 RD low to address float 0 0 ns tWHLH 15, 16 RD or WR high to ALE high 23 103 tCLCL–40 tCLCL+40 ns External Clock tCHCX 18 High time 20 20 tCLCL–tCLCX ns tCLCX 18 Low time 20 20 tCLCL–tCHCX ns tCLCH 18 Rise time 20 20 ns tCHCL 18 Fall time 20 20 ns Shift Register tXLXL 17 Serial port clock cycle time 750 12tCLCL ns tQVXH 17 Output data setup to clock rising edge 492 10tCLCL–133 ns tXHQX 17 Output data hold after clock rising edge 8 2tCLCL–117 ns tXHDX 17 Input data hold after clock rising edge 0 0 ns tXHDV 17 Clock rising edge to input data valid 492 10tCLCL–133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC51 and 80C31 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interface. 5. Parts are guaranteed to operate down to 0Hz. |
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